In data communication and synchronization applications, a clock signal synchronizes and regulates the processing of data signal. For data processing, the clock signal is typically extracted from an incoming digital (e.g., binary) data signal in a digital signal format such as non-return-to-zero (NRZ) format. These applications generally use a phase-locked loop (PLL) system to recover the clock signal from the arriving digital data signal.
Conventional PLLs are typically implemented in integrated circuit systems by using low Q oscillators to reduce cost. However, since low Q oscillators are highly sensitive to variations in temperature and/or process, a variation in temperature and/or process can cause a variation in the frequency of the oscillators. Due to the frequency variation, the conventional PLLs may not lock on to the incoming digital signal properly. Thus, recovery of a clock signal from the incoming signal becomes more difficult. To overcome such frequency variation, PLL systems require a larger pull-in (i.e., capture) range, which is the range of frequencies over which the PLL systems can acquire lock with the incoming data signal.
In addition, noise signals are often generated and detected during the transmission and reception of an incoming signal. In conventional PLL systems with low Q oscillators, the pull-in range of a conventional PLL system is not significantly larger than the noise bandwidth. When a filter is used to filter out the noise, the filter further reduces the pull-in range. The inadequate pull-in range has thus presented a significant problem in recovering a clock signal from the incoming data signal.
To address the clock recovery problem, circuit designers have used an acquisition device such as a frequency detector to assist in locking on an incoming signal by increasing the lock-in range. For example, Ansgar Pottbacker and Ulrich Langmann describe a phase and frequency detector IC that implement a clock recovery scheme in an article entitled "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s," which is incorporated herein by reference in its entirety.
Prior Art FIG. 1 illustrates a conventional PLL system 100 that employs a phase and frequency detector as described in the Pottbacker article. The PLL system 100 includes an phase detector 102, a quadrature phase detector 104, a frequency detector 106, a summer 108, a filter 110, and a voltage-controlled oscillator (VCO) 112. The phase detector 102 and the quadrature phase detector 104 receive an identical NRZ input data signal.
The VCO generates a VCO signal. The phase detector 102 receives the VCO signal while the quadrature phase detector 104 receives the VCO signal that has been delayed between 45 and 135 degrees in phase. The phase detector 102 and the quadrature phase detector sample the VCO signal and the delayed VCO signal, respectively, at every transition of the input data signal. If the frequencies of the VCO and the input data signal are unequal, the phase detectors 102 and 104 generate well known beat note signals Q1 and Q2, repectively.
The frequency detector 106 receives the beat note signals Q1 and Q2 for processing. The frequency detector 106 generates a frequency difference signal Q3 as its output. The summer 108 receives and sums the beat note signal Q1 and the frequency difference signal Q3. The filter 110 receives the summed signal and generates a DC component that drives the VCO 112 toward lock.
Unfortunately, the PLL system 100 may not lock properly to the input data signal. For example, when the beat note signal Q1 and the difference signal Q3 are not equal and opposite amplitude to cancel each other out, the PLL system may not properly drive the VCO frequency toward lock. In addition, the operation of the frequency detector 16 is relatively slow compared to the phase detectors 102 and 104. This may lead to a 180 degrees out-of phase locking of the PLL system 100 to the input data signal, which in turn lead to loss of the input data.
A PLL system addressing these problems is disclosed in U.S. Pat. No. 5,694,088 by Andrew Dickson entitled "Phase Locked Loop with Improved Phase-frequency Detection," which is incorporated herein by reference in its entirety. The PLL system by Dickson generates a squelch signal to squelch appropriate half cycles of the beat note signal Q1. A filter integrates the squelch signal to drive the VCO in the proper direction toward lock. However, this PLL system can be costly to implement due to the extra hardware associated with the generation and use of the squelch signal.
Furthermore, the conventional frequency detector may not generate an unambiguous difference signal Q3. In particular, the conventional frequency detector generally allows the PLL system 100 to lock on only one clock edge. For example, if the quadrature phase detector 104 generates "1" as the beat note signal Q2, then the frequency detector 106 will output "0" as Q3. In contrast, if the quadrature phase detector outputs "1" as Q2, the frequency detector 106 outputs -Q1, which is the inverted output signal Q1 of the phase detector 102. When the inverted output signal of the phase detector 102 becomes larger than the original phase detector signal, then the polarity of the control loop circuit changes. Accordingly, the PLL system is stable on only one clock edge. This often leads to the PLL system 100 locking on the wrong edge of the clock. In addition, the conventional frequency detector and the PLL system described in in U.S. Pat. No. 5,694,088 by Andrew Dickson generates digital signal that has to be added with the phase detector output signal Q1 to get the proper offset.
Thus, what is needed is a frequency detector that can reliably and unambiguously detect and generate a frequency difference signal without the complexity of conventional frequency detector circuits. In addition, what is needed is a frequency detector that can avoid locking on the wrong clock edge while providing a DC offset signal at its output.